Created by Vikas N Kumar / Selective Intellect
Follow us on Twitter at @_vicash_ / @selectintellect
© 2014. Selective Intellect LLC. All Rights Reserved.
Pegex
for grammar parsingMoo
for backend code generation managementAlien::gputils
for assembly compiling to
.hex
gpsim
for SimulationPegex::Grammar
sub-class generated by
Pegex::Parser
VIC::Grammar
Pegex::Parser
invokes abstract class
Pegex::Receiver
VIC::Receiver
got_$RULE
invokedfinal
VIC::Receiver
VIC::Grammar
and VIC::Receiver
use base class
Pegex::Base
which is just Mo
final
callback
Main
blockVIC::PIC::*
classesMoo::Role
Moo::Role
used like an interface in VIC™VIC::PIC::Roles::*
is a list of all different rolesVIC::PIC::Functions::*
with
on the names of the VIC::PIC::Roles::*
and VIC::PIC::Functions::*
package VIC::PIC::Roles::Timer;
{
use Moo::Role;
requires qw(timer_enable timer_disable timer timer_prescaler
wdt_prescaler timer_pins);
}
package VIC::PIC::Functions::Timer;
use Carp;
use Moo::Role;
sub timer_disable {
my ($self, $tmr) = @_;
return unless $self->doesroles(qw(Timer Chip));
unless (exists $self->timer_pins->{$tmr}) {
carp "$tmr is not a timer.";
return;
}
unless (exists $self->registers->{OPTION_REG} and
exists $self->registers->{INTCON}) {
carp $self->pic->type,
" does not have the register OPTION_REG/INTCON";
return;
}
return << "...";
\tbanksel INTCON
\tbcf INTCON, T0IE ;; disable only the timer bit
\tbanksel OPTION_REG
\tmovlw B'00001000'
\tmovwf OPTION_REG
\tbanksel $tmr
\tclrf $tmr
...
}
package VIC::PIC::P12F683;
{
use Moo;
extends 'VIC::PIC::Base';
# role CodeGen
has type => (is => 'ro', default => 'p12f683');
has include => (is => 'ro', default => 'p12f683.inc');
# .... MORE RULE IMPLEMENTATIONS....
my @rolenames = qw(CodeGen Operators Chip GPIO
ADC ISR Timer Operations CCP Comparator);
my @roles = map (("VIC::PIC::Roles::$_",
"VIC::PIC::Functions::$_"),
@rolenames);
with @roles;
}
gputils
Alien::gputils
gpsim